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AR# 29122

Architecture Wizard 9.2 - Virtex-4 DCM input clock frequency range does not match data sheet


In Architecture Wizard 9.2, the DCM input clock frequency ranges do not match the data sheet. Architecture Wizard will give an error about the input clock frequency range. This error message will not allow a DCM to be generated unless the input clock frequency is within the range given in the error message. The data sheet values are correct.


Solution 1

To work around this issue, DCMs can be manually instantiated. This is done as follows:

1. In ISE 9.2, select Edit -> Language Templates.

2. Expand either the VHDL or Verilog.

3. Expand "Device Primitive Instantiation," "FPGA," "Clock Components," "Digital Clock Manager (DCM)".

4. Select either the DCM_ADVor DCM_BASE, depending on the functionality needed. Functionality can be found in the 9.2 Software Manual, in the Virtex-4 Libraries Guide for HDL designs. http://toolbox.xilinx.com/docsan/xilinx92/books/docs/v4ldl/v4ldl.pdf
5. Use this as a base template to instantiate the DCM.

Valid ranges are documented in the Virtex-4 Data Sheet: DC and Switching Characteristics under "Switching Characteristics"->"DCM and PMCD Switching Characteristics."


Solution 2

Create the DCM with the desired parameters using a clock that is within the range the wizard will accept, and modify the created HDL code.

1. Enter a range that Architecture Wizard accepts as valid (above 32 MHz).

2. Proceed entering parameters as desired.

3. If you would like to use the CLKFX output, enter a value of 2 for multiply and 1 for divide.

4. Generate the DCM.

5. Open the created VHD/V file and modify the instantiation generic map (not the component declaration) in the case of a VHDL generation, or the defparams in the case of Verilog.

a. Make sure that the CLKIN_PERIOD is set to the proper value for the input clock frequency desired.

b. Set the CLKFX_MULTIPLY and CLKFX_DIVIDE parameters to the values desired for the output frequency and within the limits specified in the DC and Switching Characteristics for the part targeted.

6. Save the modified VHD/V file under a new filename.

7. Add the modified VHD/V file to the project.

8. Use the instantiation template to instantiate the modified DCM module in your design.

Once again, be sure that the values that changed in the VHD/V file are valid according to the data sheet in Solution 1.

AR# 29122
Date 12/15/2012
Status Active
Type General Article
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