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AR# 29126

9.2i XST - "INTERNAL_ERROR:Xst:cmain.c:3111:1.8.6.1"

Description

Keywords : Internal, error, Verilog, XST, cmain

I get an Internal error when I synthesize my design using XST. Why?

Solution

One of the possible cause for the internal error is due to the following construct

assign VC1[15:0] = {{2{Add0[13]}}, Add0[13:0]} + {{2{Add1[13]}}, Add1[13:0]};

To work around this issue please rewrite the code as follows

wire [15:0] tmpAdd0 = {{2{Add0[13]}}, Add0[13:0]};

wire [15:0] tmpAdd1 = {{2{Add1[13]}}, Add1[13:0]};

wire [16:0] tmpVC1 = tmpAdd0 + tmpAdd1;

assign VC1[15:0] = tmpVC1[15:0];

Note: Xilinx is actively trying to provide better error messages to help you debug the issue. Xilinx recommends that you open a webcase at:http://www.xilinx.com/support/clearexpress/websupport.htmand provide a test case that reproduces the problem so that it can be fixed in a future release.

AR# 29126
Date Created 03/06/2008
Last Updated 12/15/2012
Status Active
Type General Article