The Virtex-5 CRC32 and CRC64 blocks do not behave as described in the GTP RocketIO Users Guide (UG196 v1.3).
This Answer Record summarizes common issues with the CRC blocks.
The CRC64 and CRC32 simulation models clock all inputs into the model at the same time.
If CRCCLK, CRCIN, CRCDATAVALID, and CRCRESET transition at the same time, the CRCOUT value might not be correct.
The CRC Wizard v1.1 works around this problem by delaying the CRC interface ports relative to the clock.
Another way to work around this issue is to register the inputs with CRCCLK before they enter the CRC block.
Figure 8-3 in (UG196) v1.3 does not contain the correct CRC timing diagram. The corrected timing diagram is:
The important difference between the correct timing diagram and the one in (UG196) v1.3 is that when CRCDATAVALID and CRCRESET are both High, CRCIN is used in the CRC calculation.
This timing diagram shows how to calculate back to back CRC values.
Note that there is one clock cycle after CRCDATAVALID goes Low to allow the final CRCOUT value to be clocked out of the CRC block before the next frame starts.