We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29146

11.1 EDK - DMA does not work when cache is enabled


Keywords: coherency, DMA, master

I have a design where I am doing DMA transfer from my PLB master IP to external memory and vice versa.

The DMA works fine, but only if I disable cache. If I enable cache, it does not work.


Make sure that the cache coherency issue has been ruled out.

Please refer to the PowerPC Reference Guide for more information on cache coherency.

When initializing your source and destination buffer, flush your cache line to avoid cache coherency after each initialization. The following code snippet provides an illustration:

set_data_buffer(src_buffer, 64, 5);

set_data_buffer(dst_buffer, 64, 0);

AR# 29146
Date 04/28/2009
Status Active
Type General Article
Page Bookmarked