Compare mismatches might occur during timing simulation.
This error is not a result of an issue with the core. It is dependent on how the core is placed in devices with large unused areas, such as testing platforms. You can work around this issue by setting the clock period to 30000 for both PERIOD_OPB_CLK and PERIOD_MOST_CLK.
| AR# 29161 | |
|---|---|
| Date | 05/22/2014 |
| Status | Archive |
| Type | General Article |