UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29165

LogiCORE OBSAI v1.1 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)

Description

This Release Note is for the Open Basestation Architecture Initiative (OBSAI) v1.1 released in 9.2i IP Update 1, and contains the following information: 

- New Features 

- Bug Fixes 

- General Information 

- Known Issues 

 

For installation instructions and design tools requirements, see (Xilinx Answer 25222)

Patch is required to address critical known issues (Xilinx Answer 29194).

Solution

New Features in v1.1  

 

Supports ISE 9.2i 

 

Bug Fixes in v1. 1 

 

None. 

 

General Information  

 

None. 

 

Known Issues in v1.1 

(Xilinx Answer 29166) When simulating, warnings and errors might occur 

(Xilinx Answer 29167) GTP attribute change is needed 

 

Known Issues fixed in v1.1 Patch1 

- When RP3_01 is enabled, the FCB generated at the slave has the bit order reversed. 

 

Known Issues fixed in v1.1 Patch2 

- When the length of the frame counter is greater than the 16-bit Delta counter, the core does not respond correctly to negative Delta values. 

- Width mismatch in "dlink_rx_sync_fsm_if.vhd" causes a synthesis warning in XST.  

- FCB counter stops half a cycle too early. This causes a small error at the time the FCB is regenerated.  

To obtain a patch (either patch #1 and #2), please see (Xilinx Answer 29194).

AR# 29165
Date Created 10/28/2007
Last Updated 05/22/2014
Status Archive
Type General Article