We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29173

LogiCORE FIFO Generator v4.1 - In VHDL behavioral simulation, DOUT powerup as "x" until the first word falls out


For the First-Word-Fall-Through configurations with Embedded Registers, in the VHDL behavioral model simulation, DOUT powers-up as "x" until the first data falls out. The power-up value of DOUT is correct in the Verilog behavioral model.


This issue is seen only in behavioral simulation. Please use structual simulation model instead of behavioral simulation. The structural model can be generated by selecting Core Generator GUI, under Project Option, Generation Tab.

AR# 29173
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked