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AR# 29178

9.1i Timing Analyser - Does not take into account the input registers of a multiplier for Spartan-3A

Description

The following inferred multiplier produces incorrect timing results with Spartan-3A device

process (clk)

begin

if rising_edge (clk) then

A_int <= A;

B_int <= B;

S_int <= A_int * B_int;

S <= S_int;

end if;

end process;

A_int, B_int and S_int are placed inside the HARDMULT.

The timing analyzer doesn't take into account the input registers. The only timing it knows is Tmsdck_P, while we should see Tmsdck_A or Tmsdck_B. This occurs only when targeting Spartan-3A. The issue does not exist for Spartan-3E.

Solution

This is a known issue and is fixed in ISE 9.2.02i.

AR# 29178
Date Created 10/28/2007
Last Updated 01/18/2010
Status Archive
Type General Article