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AR# 29189

13.1 Timing Analyzer - Why is DCM Phase Shifting ignored when OFFSET ... HIGH | LOW is specified?


In my design, the system clock goes through a DCM and has a fixed phase shift. When specifying the constraint as shown below, the paths covered by Offset In constraint always have a zero clock arrival time, instead of the phase shift value. Why does this happen?

INST "sysclk_dcm" PHASE_SHIFT = 64;
NET "sysclk" TNM_NET = "sysclk";
TIMESPEC "TS_sysclk" = PERIOD "sysclk" 5 ns;
OFFSET = IN 4.5 ns VALID 4 ns BEFORE sysclk HIGH;


The HIGH keyword on the OFFSET constraint truncates the rising clock arrival time to zero, and the LOW keyword truncates the falling clock arrival time to zero. HIGH | LOW can be used to override the HIGH | LOW keyword defined on the PERIOD constraint. Xilinx recommends the use of the RISING/FALLING keywords instead of the HIGH/LOW keywords for DDR designs.

To make it count the Fixed Phase shift value for the clock arrival time, you can replace the HIGH | LOW keyword for RISING | FALLING keywords for Offset constraint.

For more information on constraints and analysis, seethe"Timing Constraints User Guide" (UG612)
AR# 29189
Date 12/15/2012
Status Active
Type General Article
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