We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29193

9.2i CORE Generator - Known Issues for CORE Generator 9.2i


Keywords: interface, COREGen, IP, cores, GUI, software, integration

This Answer Record contains a list of known issues involving CORE Generator in the ISE 9.2i Release.

For IP-specific information, see the Xilinx IP web page:


Current Known Issues

(Xilinx Answer 20478) - A COREGen project created on a PC does not behave properly on Linux and Solaris systems
(Xilinx Answer 21955) - An error occurred while running Java. This may be due to memory limitations
(Xilinx Answer 22548) - "WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst <instance name> of Component <core name>"
(Xilinx Answer 22549) - When running Manage Cores through Project Navigator on Linux 32, IP cores cannot be customized when Java memory is set to 2048 or above
(Xilinx Answer 22600) - Selecting View Version information for a specified IP Core results in "ERROR:sim:165 - Could not find version info"
(Xilinx Answer 22601) - Fragmented or seemingly incomplete error messages are being displayed in the COREGen console window
(Xilinx Answer 22605) - Project -> Project Options... "Preferred Implementation Files" label is not fully visible on Solaris and Linux platforms
(Xilinx Answer 23395) - Some IP cores provided in CORE Generator have incomplete or inaccurate simulation models
(Xilinx Answer 24114) - "WARNING:Sim:NetListWriters - The output generated using -ecn option when targeting Virtex-5 currently does not create a simulatable formal verification netlist"

Known Issues fixed in ISE 9.2i SP1

(Xilinx Answer 25227) - Synthesis of the opb_usb2_device core results in the following error: "Exception in thread "main" com.xilinx.sim.exception.ElaborationException"
(Xilinx Answer 25228) - Generating the Serial RapidIO Core in batch mode causes a segmentation fault
(Xilinx Answer 25229) - PCI cores cannot be generated on WinXP64 or Win 2003: "java.util.zip.ZipException: Not enough disk space in path"
(Xilinx Answer 25369) - Generated core does not appear in ISE project; error message occurs: "CORE Generator generated file <corename>/simulation/glbl.v does not exist in the project directory!"

Known Issues fixed in ISE 9.2i SP2

(Xilinx Answer 29105) - PCI-based IP Cores cannot be generated on Windows Vista
AR# 29193
Date 04/08/2009
Status Archive
Type General Article