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AR# 29243

10.1 Timing Analysis - Possible Timing issues when gating clocks


Keywords: Gating Clocks, Timing, Constraints

Due to the order of the timing constraint, you might have some timing issues when gating clocks. The order of the constraints in the PCF file dictates the priority of the constraints unless the PRIORITIES keyword is used.

When you are gating clocks, 1 clock is connected to the D input of the flip-flop and 1 clock is connected to the clock input of the flip-flop. To obtain a proper timing analysis, you would like the constraint for the clock driving the clock input of the flip-flop to be analyzed, but due to the PCF file order, this does not always happen. If the clock connecting to the D input has priority in the PCF file, it will be taken as the constraint to analyze this path which gives incorrect results.


Use the PRIORITIES keyword in the UCF file when defining the constraint or order the constraints appropriately. This works for two input clocks but not for clock on the output of a DCM as these constraints are automatically generated.

Clocks constraints automatically generated at the output of a DCM - As these constraints are generated by the tool, you cannot change the priority. The workarounds are:

1. You add the PERIOD constraint to the output of the DCM and not to the input. Hence, you are deciding the priority.
2. Modify the PCF file to reorder the constraints or add the PRIORITIES keyword. This has the disadvantage that it will be regenerated every time you rerun the tools. You can add these constraints outside the SCHEMATIC START/END comments, and they will only be removed when running a clean-up project files.

This issue will be resolved in ISE 10.1
AR# 29243
Date 04/29/2008
Status Archive
Type General Article
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