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AR# 29282

9.1isp2 EDK/IP - Mapping DSOCM BRAM in UltraController II


Keyword: DSOCM BRAM, UltraController, II, address map

I am designing with Ultra-Controller II. When I map a DSOCM BRAM within the top 128 MB of the address range, I encounter unstable behavior when read/writing to the DSOCM memory.


Ultra-Controller II uses cache-based processing and is automatically set up to cache the upper 128 MB of memory (0xF800 0000 - 0xFFFF FFFF). However, PPC405 OCM controller is non-cacheable and might result in a potential memory problem when the connecting memory is mapped to a cacheable region in the PPC.

To resolve this problem, please make sure the address range of the DSOCM memory is not in the upper 128 MB of the memory space.

AR# 29282
Date 12/15/2012
Status Active
Type General Article
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