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AR# 29294

Block Plus Endpoint v1.9.3 for PCI Express - In simulation, core is not training until about 400 microseconds. Is this correct?


The Block Plus Endpoint for PCI Express should link up (trn_lnk_up_n = 0) at around 250 microseconds in simulation. 

It has been found that in some cases the link up might take about 400 microseconds.  


Note: If you are using v1.9.1, see (Xilinx Answer 32031)


The GTP/GTX simulation model was updated to not drive X's when simulating electrical idle. 

When using 10.1sp3 or later, it is not necessary to include this work-around. 


However, if you are simulating an x1 core using Verilog, there is a mistake in the board.v file that might cause some problems.  

Starting in the v1.7 Core release, the Verilog version was updated with code to work around the original problem of the GTP/GTX model driving X's. 

However, the x1 board.v file is incorrect and should be modified to reduce simulation time.

The current file contains these assignments: 


.pci_exp_rxn( ((cor_pci_exp_txn[0] === 1'b1) && (cor_pci_exp_txp[0] === 1'b1)) ? 1'bx : cor_pci_exp_txn[0]), 

.pci_exp_rxp( ((cor_pci_exp_txn[0] === 1'b1) && (cor_pci_exp_txp[0] === 1'b1)) ? 1'bx : cor_pci_exp_txp[0]) 


These assignments should be changed to: 


.pci_exp_rxn( ((cor_pci_exp_txn[0] === 1'bx) && (cor_pci_exp_txp[0] === 1'bx)) ? 1'b1 : cor_pci_exp_txn[0]), 

.pci_exp_rxp( ((cor_pci_exp_txn[0] === 1'bx) && (cor_pci_exp_txp[0] === 1'bx)) ? 1'b1 : cor_pci_exp_txp[0]) 


Not changing these lines in the x1 board.v file might result in longer than normal simulation times. 


Using Third-Party BFMs 


The GTP/GTX model will still drive X's on the bus from when GTP[X]RESET is deasserted until RESETDONE asserts as shown in this figure. 




This happens immediately after sys_reset_n deasserts.

If this causes a problem with your BFM model, then possibly hold it in reset until RESETDONE asserts or add a similar work-around to the above back to the instantiation of the core and connection between the BFM and the DUT. 




Here is an example for Verilog. 

Replicate this for as many lanes as are in use. 



.BFM_rxn( ((cor_pci_exp_txn === 1'bx) && (cor_pci_exp_txp === 1'bx)) ? 1'b1 : cor_pci_exp_txn), 

.BFM_rxp( ((cor_pci_exp_txn === 1'bx) && (cor_pci_exp_txp === 1'bx)) ? 1'b1 : cor_pci_exp_txp), 






Here is a similar example for VHDL x1: 


signal cor_pci_exp_txn_fix : std_logic_vector; 

signal cor_pci_exp_txp_fix : std_logic_vector; 



BFM_INST : MY_BFM port map ( 

BFM_rxn => cor_pci_exp_txn_fix,  

BFM_rxp => cor_pci_exp_txp_fix,  




process (cor_pci_exp_txn, cor_pci_exp_txp) 



if ( ((cor_pci_exp_txn = 'X') or (cor_pci_exp_txn = 'U') ) and ((cor_pci_exp_txp = 'X') or (cor_pci_exp_txp = 'U') )) then 

cor_pci_exp_txn_fix <= '1'; 

cor_pci_exp_txp_fix <= '1'; 


cor_pci_exp_txn_fix <= cor_pci_exp_txn; 

cor_pci_exp_txp_fix <= cor_pci_exp_txp; 

end if; 


end process; 


Note: This does not affect simulations with the Xilinx DSPORT because the DSPORT is still going through its reset sequence during this time. 


Revision History 

03/02/2009 - Updated to reflect GTP/GTX models fixed and third-party BFM information. 

03/23/2008 - Updated to reflect v1.6.1 for 10.1 release. 

11/14/2007 - Added VHDL work-around. 

09/18/2007 - Initial Release of AR.

AR# 29294
Date 11/25/2014
Status Active
Type General Article
  • Endpoint Block Plus Wrapper for PCI Express
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