This Release Notes and Known Issues Answer Record is for the Virtex-4 and Virtex-II Pro Aurora v2.8, released in 9.2 IP2, and contains the following information:
- New Features
- Bus Fixed in this version
- Known Issues
- ChipScope Pro cores can be added to the Aurora Core from the Xilinx CORE Generator tool.
- Aurora Core has been enhanced to include timer-based Simplex mode. This Simplex mode does not rely on sideband signals.
Bugs Fixed in v2.8
- LANE_INIT_SM has asynchronous inputs to a synchronous state machine.
- GT11_INIT has an asynchronous input to a synchronous state machine.
- LogiCORE Aurora 2.6 Documentation (UG061).
- Improperly handled clock domain crossing causes lane to not come up.
- Removal of MTI_LIBS variable setting from ModelSim "do" file.
- Enhance Aurora Wizard MGT selection in GUI.
- The LX220T and LX85T reference designs were not added to the Wizard at the time of release. To target these devices, change the CORE Generator project options to a different device and manually adjust GTP location in the generated UCF file.