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AR# 29432

9.X ISE Simulator (ISim) - "ERROR:Simulator:29 - at 0 ns : File ddr2.v : Gate array sizes differ."


When simulating a MIG design in ISE Simulator (ISim), the following error occurs:

"ERROR:Simulator:29 - at 0 ns : File ddr2.v Line 417: Gate array sizes differ.

ERROR:Simulator:34 - Elaboration failed."

How do I resolve this error and simulate in ISim?


ISE Simulator (ISim) is processing the replication operation {DQS_BITS{out_en}} as more than two bits in this bufif1 and, consequently, generating the "Gate array sizes differ" error.

To work around this issue, create a temporary signal for the replication and then use the temporary signals as the output enable of the bufif1.


Line in question:

bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});

Re-written as:

wire [DQS_BITS - 1 :0 ] test;

assign test = dqs_out_en_dly & {DQS_BITS{out_en}};

bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, test);

This issue is fixed in ISE 10.0.

The complete work-around for the above error in MIG simulations is as follows:


bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});

bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});

bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});

bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});

bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});


wire [DQS_BITS-1:0] buf_dqs_en;

wire [DM_BITS-1:0] buf_dm_en;

wire [DQS_BITS-1:0] buf_dqs_n_en;

wire [DQS_BITS-1:0] buf_rdqs_n_en;

wire [DQ_BITS-1:0] buf_dq_en;

assign buf_dqs_en = dqs_out_en_dly & {DQS_BITS{out_en}};

assign buf_dm_en = dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}};

assign buf_dqs_n_en = dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}};

assign buf_rdqs_n_en = dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}};

assign buf_dq_en = dq_out_en_dly & {DQ_BITS {out_en}};

bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, buf_dqs_en);

bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, buf_dm_en);

bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, buf_dqs_n_en);

bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, buf_rdqs_n_en);

bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, buf_dq_en);

In addition, the following steps might need to be followed to support MIG ISim simulation:

- Place the DDR2 memory model parameters file into the PAR directory.

- Open up the DDR2 memory model parameters file and set the necessary defines (this depends on what you are simulating; open "sim.do" to obtain your own parameters), for example:

`define x512Mb

`define sg3

`define x8

- Label the for-loops in the sim_tb_top generate statements (there are multiple). Note that "begin" might be on the line below in the code and not on one line as shown here.

For example from Line 249:

ORIGINAL: for(i = 0; i < DQS_WIDTH/2; i = i+1) begin

NEW: for(i = 0; i < DQS_WIDTH/2; i = i+1) begin: u0
AR# 29432
Date 07/22/2010
Status Archive
Type General Article