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AR# 29447

LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder Core. 

The following information is listed for each version of the core: 

  • New Features 
  • Resolved Issue
  • Known Issues 

LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder Lounge: 

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DO-DI-CTC-80216E-DEC


The 802.16E Convolutional Turbo Code (CTC) Decoder core has been discontinued. Please see the Following PDN: 

http://www.xilinx.com/support/documentation/customer_notices/xcn14010.pdf

Solution

General LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder Issues 

- How are the scaling and puncturing processes carried out on the CTC Decoder? See (Xilinx Answer 25108)

 

LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder v4.0 

New Features 

- ISE 11.2 software support 

- Virtex-6 and Spartan-6 support 

Resolved Issues 

None 

Known Issues 

(Xilinx Answer 36084) - 1 SISO does not work if you put 2400, 24 and 2400 blocks into the decoder. How can I work around this?  

 

LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder v3.1 

New Features 

- ISE 10.1 software support 

Bug Fixes 

CR472797- BUFG's are inserted in the path of the synchronous reset when the number of soft input/extrinsic bits is equal to eight, causing the clock speed performance to drop. 

Known Issues 

- N/A 

 

LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder v3.0 

Initial Release in ISE 9.2i IP Update 2 

New Features 

- First release available in CORE Generator 

- Supports all interleaver block sizes of the CTC OFDMA PHY mode including the HARQ and IR HARQ modes: 24, 36, 48, 72, 96, 108, 120, 144, 180, 192, 216, 240, 480, 960, 1440, 1920, and 2400 pairs 

- Performs parallel processing with parameterizable number of SISO's to achieve high throughput and reduce latency 

- Supports dynamic block size switching without interruption 

- Programmable number of iterations dynamically changeable per block 

- Adaptive rate change via puncturing interface 

- Uses MAX-LOG-MAP algorithm with extrinsic scaling 

- Parameterizable options for soft data input and extrinsic bits 

- Clock speed exceeds 162 MHz in Virtex-4 speed grade 

-10 and 196 MHz in Virtex-5 speed grade -1 

- Decoded data rate depends on block size and varies between 44 Mbps to 63 Mbps when targeting Virtex-4, and between 53 Mbps to 76 Mbps when targeting Virtex-5 (slowest speed grade, five iterations, and four SISO option) 

- Latency depends on block size and varies between 5 microseconds to 76 microseconds when targeting Virtex-4, and between 4 microseconds to 63 microseconds when targeting Virtex-5 (slowest speed grade, five iterations, and four SISO option) 

- Fully synchronous design with single clock domain 

- Double buffered input to accommodate burst or continuous data 

Bug Fixes 

- N/A 

Known Issues 

- When 8 bits is selected for the soft input data width and the extrinsic data, the core use three BUFGs and thus reduces the performance of the core. Why does this occur? See (Xilinx Answer 31116)

 

LogiCORE 802.16E Convolutional Turbo Code (CTC) Decoder v2.0 

Initial Release N/A 

New Features 

- N/A 

Bug Fixes 

- N/A 

Known Issues 

- Switching between different block size gives errors. See (Xilinx Answer 24614).

Linked Answer Records

Child Answer Records

AR# 29447
Date Created 10/28/2007
Last Updated 04/02/2015
Status Active
Type General Article
IP
  • IEEE 802.16e CTC Decoder