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AR# 29448

LogiCORE Viterbi Decoder - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE Viterbi Decoder.

The following information is listed for each version of the core:
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues
LogiCORE Viterbi Decoder Lounge:
http://www.xilinx.com/products/ipcenter/Viterbi_Decoder.htm

Solution

General LogiCORE Viterbi Decoder Issues
  • If my input data is very regular and I do not see the expected Bit Error Rate, what can I do? See (Xilinx Answer 22374).
  • How do I calculate the data rates for the LogiCORE Viterbi Decoder operating in various configurations? See (Xilinx Answer 22641).

LogiCORE Viterbi Decoder v8.0

  • Initial Release in ISE 13.4

New Features

  • ISE 13.4 software support
  • AXI interface

Supported Devices

  • Zynq-7000*
  • Virtex-7 XC XT/HT/T
  • Virtex-7 -2L XC XT/T
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Kintex-7 XC
  • Kintex-7 -2L XC
  • Artix-7 XC
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XQ LX
  • Spartan-6 -1L XC LX

Resolved Issues

  • None

Known Issues

  • None

LogiCORE Viterbi Decoder v7.0

  • Initial Release in ISE 11.2

New Features
  • ISE 11.2 software support
  • Virtex-6 and Spartan-6 FPGA support
  • Asynchronous reset input removed
  • Speed option for Virtex-5 FPGA removed

Resolved Issues
  • CR442529: Design fails when two Viterbi Decoders are instantiated on a Virtex-5 device
  • Naming conflict on packing caused failure in the mapper.

Known Issues
  • CR 580351 - Why am I unable to change the traceback length in the GUI for the IP CORE Generator 12.3? See (Xilinx Answer 38797).

LogiCORE Viterbi Decoder v6.2
  • Initial Release in ISE 9.2i IP Update 2

New Features
  • ISE 9.2i software support

Resolved Issues
  • CR442529: Design fails when two Viterbi Decoders are instantiated on a Virtex-5 device
    • Naming conflict on packing caused failure in the mapper
  • BER performance with best state on Virtex-5
    • Best state selection was not optimal
  • CR449260: Packet Options
    • Incorrect delay on packet start signal

Known Issues
  • How can I extend the data format for soft coding beyond the three bits listed in table 1 of the Viterbi data sheet? See (Xilinx Answer 29940).
  • Why does the latency in simulation not tie up with the latency equations in the data sheet? See (Xilinx Answer 31263).
  • How can the latency for the core be determined? See (Xilinx Answer 31275).

LogiCORE Viterbi Decoder v6.1
  • Initial Release in ISE 9.1i IP Update 3

New Features
  • Support added for:
    • Spartan-3A DSP
    • ISE 9.1i

Bug Fixes
  • CR 431791 : For constraint length 9, the BER performance is not optimal at high SNR; the BER plot shows an error floor
  • CR 435735 : In serial mode, if the ND signal is not periodic, the Viterbi Decoder v6.0 does not work correctly

Known Issues

Linked Answer Records

Child Answer Records

AR# 29448
Date Created 10/28/2007
Last Updated 05/20/2012
Status Active
Type Known Issues
IP
  • Viterbi Decoder