We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 29449

LogiCORE Fast Fourier Transform (FFT) v3.2 - Why do the timing diagrams not show the 3 clock cycle delay of the indexing signals?


Keywords: ISE, LogiCORE, FFT Compiler, FFT, xFFT, Fast, Continuous, Burst, Loop, Loop Engine, Radix 4, Radix 2

Why do the timing diagrams not show the 3 clock cycle delay of the indexing signals?

In the FFT v3.2 (DS260 January 11, 2006) data sheet Figure 12 shows the situation we are using with start and unload held high. It also shows loading frame A with the index and RFD de-asserting at the same time. Clearly this is incorrect if the data should be presented 3 clock cycles after the index it matches. Also the core is still ready for data for another 3 clock cycles after RFD has de-asserted. From a customer's point of view you would assume the RFD to be asserted when the core is actually ready for data.


It should be noted that many of the figures in the data sheet, such as Figure 12 are intended to show the timing of entire frames. and do not show the small skews between signals which occur at the start and end of frames, such as the RDF and RDY signals.

This note has been added to the Datasheet for the FFT v4.0 and beyond.

Please See (Xilinx Answer 29209) for a detailed list of LogiCORE Fast Fourier Transform (FFT) Release Notes and Known Issues.
AR# 29449
Date 09/25/2007
Status Archive
Type General Article