Why can I not achieve the performance and area number for some of the architectures as listed in the data sheet?
The performance and area numbers are wrong for the following table entries:
Table 12, Virtex-5 Radix-2 Lite: The block RAMs and DSP counts are wrong for transform lengths 256 and 1024 due to a typo. The correct values are 2 block RAMs and half the quoted number of DSPs (3 for optimize=yes, 2 for optimize=no).
Tables 24 and 25, Spartan-3E Streaming: All of the data in these tables is incorrect as these figures are actually for the Radix 2-Lite architecture.
Tables 26 and 27, Spartan-3E Radix-4: All of the data in these tables is incorrect as an implementation flow issue forced some multipliers to be implemented in fabric instead of in mult18x18s. This has made the multiplier counts too small, made the slice counts too large, and decreased the achievable clock frequency.
This has been resolved in the v4.1 data sheet.
Please See (Xilinx Answer 29209) for a detailed list of LogiCORE Fast Fourier Transform (FFT) Release Notes and Known Issues.