When I try to add an external port in MHS while running synthesis in EDK, the following error occurs:
"ERROR:HDLParsers:3621 - "system.vhd" Line 31. The basic identifier... is illegal because it ends with an underline character (VHDL IEEE 1076-2000 LRM 13.3.1)."
How can this be resolved?
To resolve this issue, make sure that, when describing the external port, there are no extra underscore characters.
Valid declaration for an external port: fpga_0_FLASH_16Mx16_Mem_A_1
Invalid declaration for an external port: fpga_0_FLASH_16Mx16_Mem_A__1