There is a long path (8 ns) from Hard EMAC to FF. This is causing timing errors for some of the designs running at 100+ MHz.
This is not a timing issue. The error exists in the Virtex-5 speed files.
The following TIG resolves the issue. This might be a work-around that could be used until the speed files fix is available.
Add the following TIG to the pcf file as a way to work around this issue.
PIN disableGTXCLK = COMP "Hard_Ethernet_MAC/Hard_Ethernet_MAC/V5HARD_SYS.I_TEMAC/SING
LE_GMII.I_EMAC_TOP/v5_emac_wrapper/v5_emac" PINNAME PHYEMAC0GTXCLK;
PIN disableGTXCLK TIG;
This problem has been fixed in the latest ISE 9.2i Service Pack, available at:
The first service pack containing the fix is ISE 9.2i Service Pack 3.