This Answer Record contains Release Notes and installation information for LogiCORE Enpoint v3.6 for PCI Express, and includes the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).
A patch is available for Virtex-5 Endpoint Soft-IP Users for PCI Express. This patch updates the GTP attributes and settings.
Please download this patch at:
Updates for the pci_exp_1_lane_32b_ep, pci_exp_4_lane_32b_ep, and pci_exp_8_lane_64b_ep Cores
These cores are delivered through CORE Generator and are updated as part of 9.2i IP Update 2.
Updates for the pci_exp_1_lane_64b_ep and pci_exp_4_lane_64b_ep Cores
If you are using "pci_exp_1_lane_64b_ep" and "pci_exp_4_lane_64b_ep," download a new ZIP file containing this update from the PCI Express Lounge at:
The ZIP file release is v3.6.
- ISE 9.2i design tools support
-Virtex-5 SXT Support
-- Limited initial part/package support
-- The Xilinx LogiCORE warranty does not cover production usage with ES silicon
- Added VHDL Testbench support for the reference design
- CR 432372: Core not transitioning from L1 to L0 to send a Completion
Fixed. Virtex-5 only issue: if the core received a Configuration Read/Write to Extended Configuration Space that is implemented by you, and the core is directed to L1 before you can respond with a Completion, then the Completion might not be sent until the core is transitioned to L0.
- CR 438168: Virtex-5 x4 core might only wait 5 microseconds between ASPM L1 requests
Fixed: if ASPM L1 Entry is enabled and the host rejects a core request to move into Active State L1, the core might only wait 5 microseconds before sending another request to move into Active State L1. The specification states that an endpoint should wait at least 10 microseconds before reinitiating a request.
- Back Annotated Timing
Back annotated timing or post-PAR functional netlist simulation run times can be extremely large. This problem is primarily due to
millisecond timeout counters in the physical layer link-training protocol.
- Timing closure with the LogiCORE Endpoint for PCI Express 8-lane Core
Timing closure with the 8-lane 64-bit Endpoint core might require multiple PAR seeds or floorplanning. Using Multi-Pass Place and Route (MPPR), you can use multiple cost tables to meet timing. For more information on using MPPR, see the "Development System Reference Guide" in the Software Manuals at:
You might also need to floorplan and add advanced placement constraints for both your design and the 8-lane 64-bit Endpoint Core to meet timing.
- Timing closure with the LogiCORE Endpoint for PCI Express 4-lane Core
Timing closure with the 4-lane 32-bit Endpoint core might require multiple PAR seeds or floorplanning. Using Multi-Pass Place and Route (MPPR), you can use multiple cost tables to meet timing. For more information on MPPR, see the "Development System Reference Guide" in the Software Manuals at:
You might also need to floorplan and add advanced placement constraints for both your design and the 4-lane 32-bit Endpoint Core to meet timing.
- Programmed Power Management and Active State Power Management
Not supported in Virtex-4 device.
Impact: PCI Express link cannot be driven to non-D0 Power Managed state. The core transmitter cannot be driven to L0s and PCI Express link cannot be driven to L1 as part of Active State Power Management.
-The core does not implement "Loopback Slave"
The "Loopback Slave" mode is mainly used for verification and test, and has no impact on normal link operation.
Impact: The core cannot be put into "Loopback Slave" mode.
- MPS change results in lost ACK/NAK from core. Changing the Maximum Payload Size might result in core failing to ACK or NAK outstanding TLPs when upstream bandwidth is fully utilized.
Impact: Can result in TLPs being resent unnecessarily.
Work-around: Host should not change MPS when there is downstream traffic that has not been acknowledged by the core.
- See (Xilinx Answer 25362) regarding choosing more than one MSI vector in the CORE Generator GUI.
- CR471591 - See (Xilinx Answer 30792) regarding the Virtex-II Pro x4 core training to x1 in simulation.
- (Xilinx Answer 32091) Downstream Port model drops completions with length 64 bytes and greater
02/03/2009 - Added AR 32091 to Known Issues
04/1/2008 Added CR 471591 to Known Issues
08/15/2008 - Added Virtex-5 rev1 patch.