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AR# 29509

9.2i EDK - ERROR:HDLCompilers:200 - ../hdl/..._wrapper.v" line 41 Target of defparam '..' does not exist


When I use the Create and Import Wizard to create a user peripheral with lower-level files in Verilog, the following error occurs:

"ERROR:HDLCompilers:200 - ../hdl/..._wrapper.v" line 41 Target of defparam '..' does not exist"

This same error occurs in PlatGen when I run synthesis in ISE flow.

How can I prevent this error from occurring?


The wrapper file is generated based off the last line of the PAO file.

For instance,

The following PAO file will generate a VHDL wrapper file:

lib user_ip_v1_00_a IntClrReg verilog

lib user_ip_v1_00_a user_ip vhdl

Whereas, the following PAO file will generate a Verilog wrapper file:

lib user_ip_v1_00_a user_ip vhdl

lib user_ip_v1_00_a IntClrReg verilog

AR# 29509
Date 12/15/2012
Status Active
Type General Article
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