The FIFO Generator v4.2 Verilog behavioral model fails for WR_DATA_COUNT (w/extra logic) in the Independent Clock FWFT configurations with asymmetric ports. When the WR_DEPTH and RD_DEPTH ratio is 1:2, 1:4, or 1:8, you may see WR_DATA_COUNT is off by about 2 or 3 consistently through simulation.
This issue has been addressed in FIFO Generator v4.3. We strongly recommend an upgrade to v4.3, but if this is not possible please use the following information:
This is an issue with Verilog simulation behavioral model only and WR_DATA_COUNT will function properly in the device.
The Verilog model will be fixed in the next version of FIFO Generator core.
The workaround is to use structural simulation model. To generate structural simulation model, open Project Options in the CORE Generator Gui. Click on Generation tab, and change simulation files to "Structural".