We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29532

LogiCORE MOST NIC v1.2 - Using the MOST NIC LogiCORE with a PLL with no LOCK indicator


The MOST NIC LogiCORE has an input signal MOST_PLL_LOCK which can be driven by external PLLs to indicate the status of clock recovery. The MOST LogiCORE can be used with external PLLs that do not have a LOCK indicator subject to the following restrictions.


If using an external PLL that does not have a LOCK indicator: 


1) The MOST_PLL_LOCK signal must be tied to VDD if not driven. 

2) Unlock events will not be indicated if the external CLOCK becomes unstable. In this condition the buffer interrupts will cease. 


When the CLOCK stabilizes again, the MOST Core will detect bad data and reset automatically, allowing normal operation to resume.

AR# 29532
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked