We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29558

9.2 AccelDSP Synthesis Tool - Hardware Cosim Simulation Fails Without First Turning Off Clock Enable Project Option


When I set the Design Flow in AccelDSP to be Hardware Co-sim, I have to turn OFF the Clock Enable Project Option.


In the 9.2.00 (build 967) release of AccelDSP, the Hardware Co-sim Flow (HW Co-sim) is selected, you must ensure that the Project Option "Clock Enable" is also set to "False." You can do this via the Project Option Menu, or via the command 


SetProjectOption -clock_enable 0 


If you do not set the Clock Enable Project Option to "False" or "0" from the command line, an incorrect netlist is built for the hardware, causing simulation failures. 


This is fixed in the 9.2.01 release of AccelDSP.

AR# 29558
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked