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AR# 29570

LogiCORE CORDIC - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE CORDIC Core.

The following information is listed for each version of the core:

- New Features
- Bug Fixes
- Known Issues

LogiCORE CORDIC Lounge:

http://www.xilinx.com/products/ipcenter/CORDIC.htm

Solution

General LogiCORE CORDIC Issues

- Software Support for the Virtex-6 Lower Power parts was added in this release, but this IP is not yet supported and cannot be generated from CORE Generator. In order to work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which will allow you to generate a place holder IP that can be regenerated when support for the Virtex-6 Lower Power parts is added in 11.3.

LogiCORE CORDIC v5.0

- Initial Release in ISE 13.3

New Features

- ISE 13.3 software support

- Support for Artix-7, Zynq, Virtex-7 Lower Power and Kintex-7 Lower Power

Supported Devices

The following device families are supported by the core for this release.

Zynq-7000*

Virtex-7
Virtex-7 XT (7vx485t)
Virtex-7 -2L
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
Kintex-7
Kintex-7 -2L
Artix-7*
Spartan-6 XC LX/LXT
Spartan-6 XA
Spartan-6 XQ LX/LXT
Spartan-6 -1L XQ LX
Spartan-6 -1L XC LX

*To access these devices in the ISE Design Suite, contact your Xilinx FAE.

Bug Fixes

- N/A

Known Issues

- N/A

Zynq-7000* Virtex-7 Virtex-7 XT (7vx485t) Virtex-7 -2L Virtex-6 XC CXT/LXT/SXT/HXT Virtex-6 XQ LXT/SXT Virtex-6 -1L XQ LXT/SXT Virtex-6 -1L XC LXT/SXT Kintex-7 Kintex-7 -2L Artix-7* Spartan-6 XC LX/LXT Spartan-6 XA Spartan-6 XQ LX/LXT Spartan-6 -1L XQ LX Spartan-6 -1L XC LX

LogiCORE CORDIC v4.0

- Initial Release in ISE 11.1

New Features

- ISE 11.1 software support

- Virtex-6, Virtex-5, Spartan-6 and Spartan-3A DSP support added

Bug Fixes

- Updated Documentation

--- (Xilinx Answer 19055) How do I keep the accuracy from being greatly reduced, when the X and Y inputs start getting small (<0.3)?
--- (Xilinx Answer 19069) Why do the Arctan (ATAN) function outputs appear to be incorrect?
--- (Xilinx Answer 15137) What format is used for the data in/out of the square root function?
--- (Xilinx Answer 32021) Why do the Translate function outputs appear to be incorrect?
- CR 325322, 422307, 449716, 468906 Square Root behavioural simulation does not function correctly.
--- (Xilinx Answer 23934) Why does the behavioral simulation for the CORDIC square root mode require 4 extra clocks after asserting the ND signal, before the data will be processed?
--- (Xilinx Answer 32072) Why does the behavioral simulation for the CORDIC square root mode work for some input values and not for others?

Known Issues

- (Xilinx Answer 29861) Why are the outputs of the Verilog structural model undefined during simulation?
- (Xilinx Answer 24827) Why are the Arctan (ATAN) phase output results wrong when the X input is negative?
- (Xilinx Answer 19055) How do I keep the accuracy from being greatly reduced, when the X and Y inputs start getting small (<0.3)?

LogiCORE CORDIC v3.0

Initial Release in ISE 6.3i IP Update 3

New Features

- Support added for Virtex-4 FPGA

- Improved documentation of quantization error

Bug Fixes

- Fixed coarse rotation module overflow for case where X=1 and Y=1

Known Issues

- (Xilinx Answer 20371) Why does the simulation output of the CORDIC fail to update when the bit width is larger than 12 bits?
- (Xilinx Answer 23934) Why does the behavioral simulation for the CORDIC square root mode require 4 extra clocks after asserting the ND signal, before the data will be processed?
- (Xilinx Answer 24827) Why are the Arctan (ATAN) phase output results wrong when the X input is negative?
- (Xilinx Answer 29055) Is it possible to use the CORDIC Core on a Virtex-5 device?
- (Xilinx Answer 29861) Why are the outputs of the Verilog structural model undefined during simulation?
- (Xilinx Answer 32072) Why does the behavioral simulation for the CORDIC square root mode work for some input values and not for others?
- (Xilinx Answer 19055) How do I keep the accuracy from being greatly reduced, when the X and Y inputs start getting small (<0.3)?
- (Xilinx Answer 19069) Why do the Arctan (ATAN) function outputs appear to be incorrect?
- (Xilinx Answer 15137) What format is used for the data in/out of the square root function?
- (Xilinx Answer 32021) Why do the Translate function outputs appear to be incorrect?

LogiCORE CORDIC v2.0

Initial Release in ISE 5.1 IP Update 2

New Features

- Users now have more control over the implementation of the core, including the ability to explicitly specify :

--- instantiation of the coarse rotation module
--- generation of x, y and phase_out outputs
--- number of iterations to be implemented
--- desired internal precision

--- instantiation of output registers
--- no pipelining
--- presence of ND input

- Input and output widths can now be configured independently to different values

- Ability to specify the format of the data_x and data_y outputs. Valid data output formats are: "signed fractional", "unsigned fractional" and "unsigned integer". The data formats, "unsigned integer" and "unsigned fractional" apply to the Square-Root functional configuration only.

- The Pipelining Mode parameter now controls the pipelining of the entire core, including the coarse rotate and magnitude scaling modules, rather than for the CORDIC engine only.

- Ability to specify that the built-in multiplier be used to perform scaling.

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 16948) Why does Example 5 on Page 8, for the Arctan (ATAN) mode, have the wrong result listed for Pout?

LogiCORE CORDIC v1.1

Initial Release in ISE 5.1i IP Update 1

New Features

- N/A

Bug Fixes

- CR154033: Fixed the phase offset error when using Pi-Radian angle format

- Fixed the convergence of the Hyperbolic Functions (SINH, COSH and ATANH)

- CR147034: Modified the behavioral model to compile with NC-VHDL

Known Issues

- (Xilinx Answer 16114) During a Synopsis VHDL analyzer compilation, an error reports "Analysis Parsing VHDL-481"
- (Xilinx Answer 16161) "ERROR:Place - Structured logic associated with an F6 configuration could not be placed..."

LogiCORE CORDIC v1.0

Initial Release in ISE 4.2i IP Update 2

New Features

- N/A

Bug Fixes

- N/A

Known Issues

- (Xilinx Answer 15197) The CORDIC v1.0 data sheet contains several errors.
- (Xilinx Answer 15198) The pipelining options of "None" and "Optimal" create the same amount of latency.
- (Xilinx Answer 15201) What type of multipliers are used when the CCM option is selected?
- (Xilinx Answer 14214) 4.2i_ip2 CORE Generator CORDIC v1_0 "Sin and Cos" function contains outputs that are the opposite of what is indicated on the data sheet

AR# 29570
Date Created 03/03/2008
Last Updated 02/12/2013
Status Active
Type General Article
IP
  • CORDIC