UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29574

LogiCORE FIR Compiler v3.0 - Why are there incorrect outputs after I reset the single multiply accumulate (MACC) engine half-band filter when the data is stored in Block Memory?

Description

Why are there incorrect outputs after I reset the single multiply accumulate (MACC) engine half-band filter when the data is stored in Block Memory?

Solution

This issue is resolved in the FIR Compiler v.3.1. 

 

This issue is due to a bug in how the data address is generated. To work around this issue, do not use the SCLR pin. 

 

See (Xilinx Answer 29138) for a detailed list of LogiCORE FIR Compiler Release Notes and Known Issues.

AR# 29574
Date Created 10/28/2007
Last Updated 05/20/2014
Status Archive
Type General Article