Description

After performing a burst transaction to OPB_SDRAM, the next transaction is incorrect. The next transaction is either a read instead of a write, or a write instead of a read.  

How do I resolve this?

Solution

This issue is not planned to be fixed. Upgrading the entire system to a MPMC-based design will also avoid this issue.  

Contact Xilinx Technical Support for more information: 

http://www.xilinx.com/support/mysupport.htm