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AR# 29599: 9.2i EDK, MPMC v3.00a - How do I upgrade a mch, opb, plb sdram, ddr, or ddr2 memory controller to the MPMC?
9.2i EDK, MPMC v3.00a - How do I upgrade a mch, opb, plb sdram, ddr, or ddr2 memory controller to the MPMC?
How do I migrate an older mch/opb/plbv34 memory controller to the MPMC?
1. Read the PLB v3.4 and OPB to PLB v4.6 System and Core Migration User Guide provided with the EDK 9.2i and later documentation. Understand the new MPMC and PLBv46-based architecture and decide which PIMs will be used to take advantage of the new architecture.
2. Note that legacy memory controllers used a big-endian I/O ordering to connect to memory that often required a pin reordering to occur on the board. MPMC uses a little-endian bit-ordering which should match bit ordering to nearly all DDR and DDR2 memories directly.
3. Decide which memory physical interface (PHY) to use. For SDRAM, the sdram PHY will be chosen. For DDR and DDR2 PHYs, to use the recommended MIG PHY requires a MIG-compliant I/O pin-out. To check for MIG compliance, generate a MIG 1.73 core with a Verilog project type, direct-clocking (if available). Then, modify one of the generated UCFs to match the existing board's pin-out, and use the "Verify my UCF" feature to reimport and check the pin-out for Virtex-4 and Virtex-5 designs. If errors occur that cannot be resolved, either respin the board with MIG-compliant pins, or choose the MPMC Static PHY option. The Static PHY does not require a MIG-compliant pin-out but will have less timing margin than the default MIG-based PHYs.
4. Consult the MPMC PHY section for information on how to use specific PHYs.
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