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AR# 29635

9.2 AccelDSP Synthesis Tool - A project file from a pre-9.2 release of AccelDSP does not set Clock Enable in System Generator flow


When I use AccelDSP 9.2.00 to open a project file from a pre-9.2.00 AccelDSP Release with the flow set to System Generator, the project option "Clock Enable" is incorrect. This results in VHDL errors in the generated Netlist from System Generator.


If you are using AccelDSP 9.2.01 or newer, the following work-around is no longer necessary because the CE option will be automatically enabled if System Generator is set for the design flow. 


Beginning in the 9.2 release, the Project Option "Clock Enable" is new and must be active for the System Generator Flow. If it is not active, the generated netlist produced by System Generator will contain incorrect syntax for the port called "CE" associated with the AccelDSP Block. This incorrect syntax will cause a parsing error in XST as follows: 


ERROR:HDLParsers - <file name>Line <nnn>. parse error, unexpected CLOSEPAR 


Normally, AccelDSP correctly sets the Clock Enable Project Option when a user changes the Flow to SystemGenerator. However, if a project from 9.1 is used and that project already has the System Generator Flow set, the Clock Enable Project Option will not be set correctly. In this case, please set the "Clock Enable" Project Option to "True" if working from the Project Option Menu, or execute the following command: 


SetProjectOption -clock_enable 1

AR# 29635
Date 05/22/2014
Status Archive
Type General Article
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