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AR# 29660

Gigabit and Tri-Mode Ethernet MAC Example Design Local Link RX FIFO - Incorrect data can be read when toggling rd_dst_rdy_n

Description

Incorrect data can be read out of the RX LL FIFO if rd_dst_rdy_n is de-asserted before the last several bytes of a frame is read. This can happen if the next frame has not yet been written into the FIFO when rd_dst_rdy_n is de-asserted, but the next frame has been written in when rd_dst_rdy_n is re-asserted. No problems will occur if rd_dst_rdy_n is always asserted when reading a frame.

This applies to the following cores: LogiCORE Gigabit Ethernet MAC v8.3, Tri-Mode Ethernet MAC v3.4, Tri-mode Ethernet MAC Wrapper (Virtex-4) v4.5, Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.3 and earlier versions.

Solution

An updated version of the rx_client_fifo.v/vhd with a fix for this issue can be downloaded from the following link:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/gig_ethernet_ll_fifo_update.zip

The fix will be released in the next version of the cores.

AR# 29660
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article