Some of the PLL output clock phase shift values provided in Architecture Wizard are incorrect. This depends on the combination of DIVCLK_DIVIDE, CLKOUTn_DIVIDE, and CLKFBOUT_MULT chosen for the PLL.
If you notice that the phase shift values chosen through Architecture Wizard are not matching the actual phase shift of the PLL output in hardware, please contact Xilinx Technical Support for assistance with determining valid phase shift values.
This issue will be fixed in 9.2i Service Pack 4 of ISE design tools through a tactical patch. Please contact Xilinx Technical Support for more information regarding this tactical patch.