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AR# 29687

9.2i Timing Analyzer/Virtes-5 - ODDR CE Timing inaccurate


The Virtex-5 ODDR and three drive registers (D1, D2 and CE) are clocked by the same clock. ODDR is working on SAME_EDGE mode. Considering CE for the falling edge data, the period constraint for net CE should be half of the period for D1 or D2. However, the period requirement for CE is the same as D1 or D2.


This issue is fixed in 10.1.

AR# 29687
Date 01/18/2010
Status Archive
Type General Article
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