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AR# 29696

9.2i sp3 Virtex-5 - My design functions correctly in timing simulation, but not in hardware


A Virtex-5 design that functions correctly in timing simulation does not function properly when put on the device.

What causes this and how do I work around it?


This issue is caused by a bug in the way that Bitgen handles LUT6_2s, and is most commonly seen when the LUT6_2 is instantiated and uses an INIT string. This problem will be fixed in Service Pack 4 for 9.2i.

If you are using Synplify or Synplify Pro 8.9, you can disable LUT6_2 usage by unchecking the "Xilinx 9.2i Compatible Mode" option on the Device tab of the Implementation Options.

AR# 29696
Date 12/15/2012
Status Archive
Type General Article
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