A Virtex-5 design that functions correctly in timing simulation does not function properly when put on the device.
What causes this and how do I work around it?
This issue is caused by a bug in the way that Bitgen handles LUT6_2s, and is most commonly seen when the LUT6_2 is instantiated and uses an INIT string. This problem will be fixed in Service Pack 4 for 9.2i.
If you are using Synplify or Synplify Pro 8.9, you can disable LUT6_2 usage by unchecking the "Xilinx 9.2i Compatible Mode" option on the Device tab of the Implementation Options.