Why does the Coregen "View Resource Utilization (Under Original Project Settings)" results differ from a ISE MAP report?
When a FIR Compiler is generated there is the ability to view resource utilization. However, an issue has arisen where the logic is removed. In order to determine the resources used it is advised to use ISE project and a top-level file. In order to get started, the port declarations can be found in the VHO file.
Please see (Xilinx Answer 29138) for a detailed list of LogiCORE FIR Compiler Release Notes and Known Issues.