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AR# 29777

9.2.03i PACE/Floorplan Editor/Synplify- Cannot assign the pins orderly to a bus signal

Description

If you would like to assign the pins orderly as follows,

d[7:0] --> d[7], d[6], d[5], d[4], d[3], d[2], d[1], d[0]

--> A3, A5, A6, A7, A8, A10, A11, A13

this is the code:

input [7:0] d/* synthesis LOC="A3, A5, A6, A7, A8, A10, A11, A13" */;

If you use Synplify as synthesis tool, the results are not the same as you would like to. See below:

d[5] --> A3,

d[1] --> A5,

d[0] --> A6,

d[3] --> A7,

d[2] --> A8,

d[4] --> A10,

d[7] --> A11,

d[6] --> A13

Solution

To work around this issue, you can use XST to synthesize the design.

AR# 29777
Date Created 03/24/2008
Last Updated 01/18/2010
Status Archive
Type General Article