The MPLB_Clk port does not have SIGIS=CLK tag in the _hdl.mpd file and this causes the MPLB_Clk to be assigned to net_gnd when building a system using Base System Builder. The problem can be resolved by editing the ".mhs" file and removing the net_gnd connection to the MPLB_Clk port and reconnecting the MPLB_Clk port to the system PLB clock source (e.g., PCIe_UserClk).
Below is a snippet in the MHS file under "plbv46_pcie" that connects the MPLB_Clk port to the system PLB clock source.
PORT MPLB_Clk = PCIe_UserClk
PORT SPLB_Clk = PCIe_UserClk
PORT SPLB_Rst = PLB_Rst
PORT REFCLK = int_ref_clk
Note the MPLB_Clk port connection uses the same clock input (e.g., PCIe_UserClk) as the SPLB_Clk port connection. This is how a customer would have to connect the clock ports on the Bridge after removing the net_gnd connection that Base System Builder applies to the MPLB_Clk port.