Does the MPMC require phase-aligned clocks? What about the relationship between the MPMC and its PIM interfaces? Do all clocks used have to be sourced from the same DCM/PLL?
For simulation, all clocks must be perfectly phase aligned for behavioral simulation. In hardware, the clocks should be phase aligned to achieve maximum timing margin; however, skew between clocks should be correctly analyzed by the Xilinx timing tools.
An example would be a system where the input clock to the DCM also clocks the PLB system bus and PLB PIM. The output of the DCM driving the memory clocks will be synchronous to the input clock, but would have some skew from the pre-DCM system clock. In simulation, this system might fail and required to be adjusted to have PLB clock phase-aligned with the memory clocks. In hardware, as long as properly constrained and meeting timing, the system would function correctly.