When synthesizing a VHDL design in Foundation F1.3, the following error may result: "Error L20/C0: #480 Constraint: The Xilinx 4ke library does not contain a latch."
The XC3000 and XC4000E architectures do not contain latches in the CLBs. In the XC3000 devices, latches are implemented with combinatorial gates which cause combinatorial feedback loops, and therefore is not advised. In the XC4000E family, there is another option for implementing latches, which is to use the on-chip CLB RAM, which will provide the same functionality as the latch, but without the combinatorial feedback loops.
In Foundation 6.0.2, the XVHDL compiler would actually infer RAM when latches were described in an XC4000/E VHDL design. In F1.3, this functionality of the XVHDL compiler disappeared, and instead, an error was issued saying that the 4ke library does not contain latches. This left many designs which once compiled fine in Foundation 6.0.2 (by inferring RAM), to not compile at all in Foundation F1.3.