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AR# 29900

MIG v2.0 - The Virtex-5 DDR2 SDRAM design might encounter a setup violation when CL=3 and AL=0 are at low frequencies

Description

A setup violation might occur when CL=3 and AL=0 are at low frequencies (typically below 200 MHz) because of the way the MIG v2.0 Virtex-5 DDR2 SDRAM reference design is constrained.

The constraint that will exhibit the setup violation is as follows:

TS_u_infrastructure_dcm_clk90 = PERIOD TIMEGRP "u_infrastructure_dcm_clk90" TS_SYS_CLK PHASE 1.668 ns HIGH 50%;

The setup violation will occur between the u_ff_phy_init_data_sel flip-flop and a block RAM. The UCF constraints need to be changed to avoid this violation.

Solution

The UCF provided with the MIG v2.0 Virtex-5 DDR2 SDRAM reference design includes FROM-TO constraints to cover multicycle paths. The paths covered are known to be difficult to meet timing, but can functionally be treated as multicycle to help meet timing.

The UCF constraints that apply in this case are:

NET "sys_clk_p90" TNM = FFS "TNM_CLK90";

INST "*/u_phy_init_0/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";

TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO "TNM_CLK90" "TS_SYS_CLK" * 4;

The TNM_CLK90 timegroup is only defined to cover flip-flops (TNM = FFS "TNM_CLK90"). However, the path in question starts from the U_FF_PHY_INIT_DATA_SEL and ends at a block RAM clocked by CLK90. Because the timegroup only covers flip-flops, this path is not included.

This path only occurs when CAS latency is set to 3 and ADDITIVE latency is set to 0, which in turn, only happens at low frequencies. Problems have been experienced below 200 MHz. It is only seen in these cases because there are parts in the code that are based on these two parameters where the FLOP -> BRAM path is implemented. For other values, the path implemented is FLOP -> FLOP which is covered by the original FROM-TO constraints.

To work around this issue, changes need to be made to the UCF to redefine the timegroups for CLK90 and CLK0. The FROM-TO paths need to go from the originating flip-flops to ALL destination flops, as well as BRAM.

Add the following to the MIG-generated UCF:

## MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace

## multicycle paths from originating flip-flop to ANY destination

## flip-flop (or in some cases, it can also be a BRAM)

## MUX Select for either rising/falling CLK0 for 2nd stage read capture

INST "*/u_phy_calib_0/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";

TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS "TS_SYS_CLK" * 4;

## MUX select for read data - optional delay on data to account for byte skews

INST "*/u_usr_rd_0/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";

TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS "TS_SYS_CLK" * 4;

## Calibration/Initialization complete status flag (for PHY logic only) - can

## be used to drive both flip-flops and BRAMs

INST "*/u_phy_init_0/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";

TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS "TS_SYS_CLK" * 4;

TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS "TS_SYS_CLK" * 4;

## Select (address) bits for SRL32 shift registers used in stage3/stage4 calibration

INST "*/u_phy_calib_0/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";

TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib_0/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";

TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;

INST "*/u_phy_calib_0/gen_cal_rden_dly*.u_ff_cal_rden_dly" TNM = "TNM_CAL_RDEN_DLY";

TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS "TS_SYS_CLK" * 4;

Comment out the existing constraints in the MIG UCF:

## MIG 2.0 constraints - doesn't cover all the paths in CL=3, AL=0 case

#NET "sys_clk_p0" TNM = FFS "TNM_CLK0";

#NET "sys_clk_p90" TNM = FFS "TNM_CLK90";

## MUX Select for either rising/falling CLK0 for 2nd stage read capture

#INST "*/u_phy_calib_0/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";

#TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0"

#"TS_SYS_CLK" * 4;

## MUX select for read data - optional delay on data to account for byte skews

#INST "*/u_usr_rd_0/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";

#TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO "TNM_CLK0"

# "TS_SYS_CLK" * 4;

## Calibration/Initialization complete status flag (for PHY logic only)

#INST "*/u_phy_init_0/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";

#TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO

# "TNM_CLK0" "TS_SYS_CLK" * 4;

#TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO

# "TNM_CLK90" "TS_SYS_CLK" * 4;

## Select (address) bits for SRL32 shift registers used in stage3/stage4

## calibration

#INST "*/u_phy_calib_0/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";

#TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO "TNM_CLK0" "TS_SYS_CLK" * 4;

#INST "*/u_phy_calib_0/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";

#TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO "TNM_CLK0" "TS_SYS_CLK" * 4;

#INST "*/u_phy_calib_0/gen_cal_rden_dly*.u_ff_cal_rden_dly"

# TNM = "TNM_CAL_RDEN_DLY";

#TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO "TNM_CLK0"

# "TS_SYS_CLK" * 4;

This issue is resolved in MIG v2.1.

AR# 29900
Date Created 12/05/2007
Last Updated 12/15/2012
Status Active
Type General Article
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