The Virtex-5 DDR1 SDRAM interface passes calibration, but the read data is corrupted after calibration. This occurs either during simulation, or in actual hardware. If this phenomenon occurs, the last data word in a group of consecutive read bursts will be incorrect.
During Stage 1 Calibration, the IDELAY taps for DQ are varied to find the optimal DQ-DQS sampling window. As soon as one or two edge(s) of this window are found, the logic calculates the correct number of IDELAY taps to decrement for optimal sampling. For frequencies around ~166 MHz, it is possible that the register that stores the value to decrement by can overflow, causing an incorrect adjustment of the DQ IDELAY taps. This problem is fixed by allocating one more bit to this register to prevent overflow.
To work around this issue, download the updated phy_calib.v/.vhd file located at:
This issue is resolved in the MIG v2.1 release.