Make External" command does not set the correct width for MPMC v4.00.a external signals">
UPGRADE YOUR BROWSER
We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:
Internet Explorer 11,
Safari. Thank you!
10.1 EDK - XPS GUI "Ports -> Make External" command does not set the correct width for MPMC v4.00.a external signals
When I connect MPMC ports to the top-level, the XPS GUI "Ports -> Make External" command does not set the correct width for MPMC external signals.
The following error occurs:
"Constructing platform-level connectivity ...
ERROR:MDT - INST:MPMC3_SDRAM_CUSTOM PORT:SDRAM_DQ CONNECTOR:fpga_0_MPMC3_SDRAM_CUSTOM_SDRAM_DQ - C:\system.mhs line 120 - 32 bit-width connector assigned to 16 bit-width port ERROR:MDT - INST:MPMC3_SDRAM_CUSTOM PORT:SDRAM_DM CONNECTOR:fpga_0_MPMC3_SDRAM_CUSTOM_SDRAM_DM - C:\system.mhs line 120 - 4 bit-width connector assigned to 2 bit-width port Completion time: 0.00 seconds ERROR:MDT - platgen failed with errors!"
How do I resolve this issue?
The XPS GUI "Ports -> Make External" command does not execute the TCL processes needed by MPMC to correctly resolve parameters which control the actual width of the port.
This is due to memory database parameters and other dependencies.
Thus, you must manually set the correct port width.
This issue is fixed in EDK 11.1.
For similar issues seen in 11.4, see
(Xilinx Answer 33935).
Was this Answer Record helpful?