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AR# 29924

9.2i EDK SP2 - plbv46_plbv46_bridge_v1_00_a, PowerPC hangs on "eieio" when writing to UART via Plb2plb Bridge

Description

The "Sl_Mbusy" signal from the plbv46_plbv46_bridge is continuously High after the first write into the "uart_lite" transmit FIFO, and therefore, the processor does not proceed with writing.

Solution

The issue has been fixed for the "plbv46_plbv46_bridge_v1_00_a", and is available in EDK 9.2i Service Pack 2 at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp 

AR# 29924
Date Created 12/10/2007
Last Updated 05/22/2014
Status Archive
Type General Article