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AR# 29939 System Generator for DSP - Why doesn't the PicoBlaze microcontroller fail to correctly acknowledge interrupts that are kept high for more than two clock cycles?


Keywords: MATLAB, Simulink, SysGen, 9.2.01, PicoBlaze, BRK, ACK

When asserting the interrupt (BRK) signal on the PicoBlaze microcontroller block in a System Generator simulation, the acknowledge signal does not respond correctly and the microcontroller does not jump into the ISR until the BRK signal is deasserted.

However, when the design is generated and a behavioral simulation is done on the System Generator HDL output, the interrupt is handled correctly.


This is a known problem with the simulation model of the PicoBlaze in System Generator and can be seen when keeping the BRK signal high for more than 2 clock cycles (this is required by the PicoBlaze specifications). The microcontroller will acknowledge the interrupt and jump into the ISR only when the BRK interrupt signal is deasserted again.

To work around this problem, a simple debounce circuit can be placed in front of the PicoBlaze block, which keeps the BRK signal high for only one clock cycle. An example of such a circuit would be 3 registers followed by an inverter block. A 3 input AND block will follow this where the 3 inputs of the AND block will be the output of the inverter, the middle register and the first register. This will deassert the BRK signal on the next clock cycle after it has been asserted and the ACK will go high 2 clock cycles later.

More details on the way the PicoBlaze microcontroller handles interrupts can be found in the PicoBlaze User Guide which can be found at the following link:

This problem will be fixed in a future release of System Generator for DSP.
AR# 29939
Date 12/12/2007
Status Active
Type General Article
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