When using the PLBv46_PLBv46_bridge core, other slaves in the system have an incorrect C_SPLB2_SMALLEST_MASTER set. For example, the MPMC PLB PIM might have the C_SPLB2_SMALLEST_MASTER set to 64 or 128 when there are 32-bit masters on the bus. Then, the MPMC PLB PIM will not respond to transactions initiated from the smaller masters, resulting in bus hangs. How do I resolve this issue?
This issue is caused by the PLB bridge not having an external C_MPLB_NATIVE_DWIDTH parameter. Instead, C_MPLB_NATIVE_DWIDTH is set internally in the VHDL to match the slave port width C_SPLB_NATIVE_DWIDTH on the other side of the bridge. Without the C_MPLB_NATIVE_DWIDTH parameter visible externally, the EDK tools cannot calculate the smallest master parameter which slaves need to be correctly parameterized.
This issue is fixed in the newest version of the PLBv46_PLBv46_bridge core to be released in EDK 10.1. Contact Xilinx Technical Support if a patch is needed.