The DDS Compiler supersedes all previously released Xilinx DDS cores, including the LogiCORE Direct Digital Synthesizer v5.0.
The DDS Compiler supersedes all previously released Xilinx Sine-Cosine Look-Up Table (Sin Cos LUT) cores, including the LogiCORE Sine-Cosine Look-Up Table (Sin Cos LUT) v5.0.
LogiCORE DDS Compiler v5.0
- New Features
- ISE 12.3 software support - AXI4-Stream interface - Supports automatic core update from DDS Compiler v4.0, v3.0, v2.1 and v2.0.
Note: DDS Compiler version 5.0 is not bit-accurate with respect to version 3.0 and earlier. In particular, first order Taylor Series Correction table entries have been optimized to improve overall accuracy. Extended range of DDS with no noise shaping may reduce DATA width requirements. The update function will aim to adjust Frequency Resolution to maintain the phase width and associated DATA width. Note that this may result in the specified Frequency Resolution parameter changing. However, as phase width is maintained, this will not affect the actual resolution of frequency or phase values. Also, there have been changes to latency, in particular to accommodate the new dynamic phase increment and phase offset options. Accumulator Latency has been removed
- Resolved Issues
- Known Issues
LogiCORE DDS Compiler v4.0
Initial Release in ISE 11.3
- ISE 11.3 design tools support - Option added to use core as Phase Generator or SIN/COS Lookup Table only. - Increased Spurious Free Dynamic Range (SFDR) from 120 dBs to 150 dBs. - Option to configure DDS using system-level parameters (SFDR and Frequency Resolution) or hardware parameters (Phase and Output Width). - Option to configure phase increment and phase offset as constant, programmable or dynamic (for modulation). - SFDR range with no noise shaping increased to 150 dBs for low frequency resolution. - Taylor Series Corrected can now be used for lower SFDR (that is >66 dBs) offering solutions which trade reduced Block RAM resources for increased XtremeDSP slices. - Taylor Series Corrected has been enhanced to avoid the potential SFDR limits described in previous data sheets. - Phase width has been reduced in multi-channel DDS to give reduced resources while maintaining frequency resolution. - PHASE_OUT now optional. - Supports automatic core update from DDS Compiler v3.0, v2.1 and v2.0.
- CR529605 For integer SFDR values the Phase Angle Width may be up to 1-bit smaller than intended, resulting in reduced SFDR by upto 6 dBs. - (Xilinx Answer 33261) - CR457411 For some latency values multi-channel phase offset channel out by one. - (Xilinx Answer 30325) - Address bus (ADDR) not registered with DATA and REG_SELECT and WE, so one cycle out. - CR529789; (Xilinx Answer 33263) - SIN/COS look-up table in DDS sometimes mapped to Block ROM when Memory Type was specified as Distributed ROM. - CR529791; (Xilinx Answer 33264) - Behavior when a programmable phase increment is written through the register interface. - CR492997 - Latency reported by GUI when Latency Configuration is Auto may be inconsistent with that of the core. - CR529794
- Why if Optimization Goal is set to Speed do I see a slight increase in resource compared with v3.0? See (Xilinx Answer 33265). - Why has the number of 18k block RAMs increased from 1 to 2 for SFDR between 102 and 120dBs? See (Xilinx Answer 33372).
- ISE 11.2 software support. - Virtex-6 and Spartan-6 device support. - Phase_Out pin added.
- Overflow, low SFDR or wrong frequency when using Taylor Correction. - CR478591 and CR489147. - Description: Overflow would cause the maximum positive value of SIN or COSINE to appear as the maximum negative value possible.
- Tool-related bit accuracy. - Version to be fixed : 11.3. - CR 506442 and (Xilinx Answer 32121). - Description: Small differences can occur between the synthesized model and behavioral model outputs. These differences do not affect SFDR or frequency. For Virtex-6 and Spartan-6 FPGAs, these differences will occur when using ModelSim as the simulator. For Virtex-5, Virtex-4 and Spartan-3ADSP FPGAs, these differences will occur when using NCSIM or ISIM as the simulator.
LogiCORE DDS Compiler v2.1
Initial Release in ISE 10.1 IP Update 0
- ISE 10.1 software support
- CR 441784 - Long generation times. - CR 437506 - Excessive simulation warnings. - CR 442806 - Rounding artifacts. - CR 439192 - Inability to specify negative frequencies. - CR 455773 - Clarification of format of DATA port entry. - CR 439197 - Correction of RDY output timing.
- Why does the phase adjustment for a multichannel implementation not work correctly? See (Xilinx Answer 30325). - Why are there mismatches between the behavioral simulation and the post-translate simulation when using ISE Simulator, NC-Sim with the CIC Compiler, DDS Compiler, or the Sine Cosine LUT IP? See (Xilinx Answer 30626). - When I use Taylor series correction, why do I occasionally see a glitch in the sine wave output which looks like an overflow from the max positive to the max negative value? See (Xilinx Answer 31420). - The output frequency range on page 3 of the GUI is greater than should be allowed according to my clock frequency. See (Xilinx Answer 31608). - After a reset, why does the RDY signal go high a couple cycles prior to the sine and cosine outputs changing values? See (Xilinx Answer 31829).
LogiCORE DDS Compiler v2.0
Initial Release in ISE 9.1 IP Update 3
- Several improvements to maximum clock rate or resource utilization compared to version 1.1. - Separation of A port into REG_SELECT and ADDR to allow optional port behavior.
- CR 430701 - Symbol does not reflect correct port widths. - CR 430711 - Schematic symbol has incorrect port widths.
- Long generation times for some configurations.
LogiCORE DDS Compiler v1.1
Initial Release in ISE 8.2i IP Update 3
- Lower slice resource utilization compared to version 1.0.
- CR 427563 - GUI gives incorrect phase increment values. - CR 427833 - Behavioral and post-translate simulation mismatch when C_USE_DSP48=1 (Maximal use of DSP48). - CR 424582 - Core fails to generate when configured for accumulator width > 32.
- Why is the behavioral simulation output incorrect when using the structural simulation model? See (Xilinx Answer 24316). - Why do the outputs not go to zero when the SCLR signal is asserted, or why are the behavioral simulation outputs X when the SCLR signal is asserted? See (Xilinx Answer 24666).
LogiCORE DDS Compiler v1.0
Initial Release in ISE 8.2i IP Update 2
- First Release. - Support for Virtex-II Pro, Virtex-4, Virtex-5, Spartan-3.