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AR# 29985

LogiCOREs Fibre Channel v3.2 and Fibre Channel Arbitrated Loop v2.2 - Cannot detect CRC errors in Virtex-5 example design

Description

The coding in the example designs for Virtex-5 could cause CRC errors to go undetected 50% of time in hardware. This affects the Fibre Channel LogiCORE v3.2 and Fibre Channel Arbitrated Loop v2.2, and earlier versions of the core. The error only affects Virtex-5; it does not affect Virtex-II Pro or Virtex-4 example designs. The code will be fixed in the next release of the cores (due out in ISE 10.1).

Solution

The issue can be resolved by making a change to the example design file FCMGT.v/vhd.

For VHDL in the file "FCMGT.vhd", the current code is:

-- sync incoming data at K28.5

sync_rxdata: process (RXUSRCLK2) is

begin

if (RXUSRCLK2'event and RXUSRCLK2 = '1') then

if (RXRESET_comb = '1') then

MSB <= '0';

else

if RXCHARISK_rev(1) = '1' then

MSB <= '1';

else

MSB <= not MSB;

end if;

end if;

end if;

end process;

This should be changed to:

-- sync incoming data at K28.5

sync_rxdata: process (RXUSRCLK2) is

begin

if (RXUSRCLK2'event and RXUSRCLK2 = '1') then

if (RXRESET_comb = '1') then

MSB <= '0';

else

if RXCHARISK_rev(0) = '1' then

MSB <= '0';

else

MSB <= not MSB;

end if;

end if;

end if;

end process;

For Verilog in the file "FCMGT.v", the current code is:

// sync incoming data at K28.5

always@(posedge RXUSRCLK2)

begin

if (RXRESET_comb == 1'b1)

MSB <= 1'b0;

else

begin

if (RXCHARISK_rev[1] == 1'b1)

MSB <= 1'b1;

else

MSB <= !MSB;

end

end

This should be changed to:

// sync incoming data at K28.5

always@(posedge RXUSRCLK2)

begin

if (RXRESET_comb == 1'b1)

MSB <= 1'b0;

else

begin

if (RXCHARISK_rev[0] == 1'b1)

MSB <= 1'b0;

else

MSB <= !MSB;

end

end

AR# 29985
Date Created 12/20/2007
Last Updated 12/15/2012
Status Active
Type General Article