We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 30004

9.2i EDK, MPMC v3.00b - All MPMC DDR2 ODT signals are asserted at the same time, enabling extra termination


All MPMC DDR2 ODT signals seem to be asserted at the same time, enabling multiple terminations. Is this correct? How do I resolve this?


Multiple independent ODT signals are generated when dual-rank memory configurations are used. This bug manifests itself by enabling both ranks termination at the same time, possibly over-terminating the memory signals. This might utilize additional power than expected. 


The existing situation might be acceptable, as ODT termination is not designed to necessarily have perfect termination, but an IBIS simulation might be necessary to guarantee acceptable SI. 


If this situation causes unacceptable SI, it can be worked around by reducing the termination strength to 150 Ohms (this will lead to an effective 75 Ohm termination).  


The eventual solution to this issue is to qualify the ODT signal with each CS signal. 


This issue is fixed starting with MPMC v4.00.a, to be released in EDK 10.1.

AR# 30004
Date 05/22/2014
Status Archive
Type General Article
Page Bookmarked