AR# 30029

LogiCORE IP FIFO Generator v4.2 - Setup/Hold time violations occur in the Unconstrained Path Report


If I check the Unconstrained Path Report in a timing analysis for the FIFO Generator Core, Independent Clock type, setup or hold violations occur on some of the unconstrained paths within the FIFO.

For example:

Hold Violation: -4.085ns (requirement - (clock path skew + uncertainty - data path))
Source: sample_fifo/BU2/U0/gen_as.fgas/normgen.flblk/clkmod/cx.wrx/pntr_gc_0_BRB1 (FF)

Destination: sample_fifo/BU2/U0/gen_as.fgas/normgen.flblk/clkmod/cx.wrx/pntr_gc_x_0 (FF)
Requirement: 0.000ns
Data Path Delay: 1.323ns (Levels of Logic = 1)
Positive Clock Path Skew: 5.194ns
Source Clock: wrclk rising at 0.000ns
Destination Clock: rdclk rising at 6.400ns
Clock Uncertainty: 0.214ns

Additionally, in a distributed memory-based FIFO core, paths similar to the followingappearin the report:

Source: sample_fifo/BU2/U0/gen_as.fgas/normgen.memblk/mem0.distinst/inst_Mram_mem5/DP (RAM)
Destination: sample_fifo/BU2/U0/gen_as.fgas/normgen.memblk/mem0.distinst/dob_i_5 (FF)

Requirement: 0.000ns
Data Path Delay: 1.624ns (Levels of Logic = 0)
Positive Clock Path Skew: 5.237ns
Source Clock: wrclk rising at 0.000ns
Destination Clock: rdclk rising at 6.400ns
Clock Uncertainty: 0.214ns

The FIFO Generator Core Users Guide indicates that PERIOD constraints on the write clock and read clock are sufficient for the core. Are these unconstrained paths a concern?


Due to the nature of the FIFO Generator Core in Independent Clocks mode, the core must pass information between separate clock domains (e.g., wrclk to rdclk). The specific paths listed here involve passing information about the read and write pointers within the FIFO. Because of the method used to construct this logic within the FIFO Core, timing violations on these paths are expected.

To work around this issue (for Block Memory-based FIFOs):

  1. Timing violation on these types of paths can be ignored in the Unconstrained Path report.
  2. If you want to keep these paths from being analyzed, Timing Ignore ("TIG") constraints can be defined in the UCF. For example:
NET "*BU2/U0/as.fgas/normgen.flblk/clkmod/cx.wrx/pntr_gc_x(*)" TIG;
NET "*BU2/U0/as.fgas/normgen.flblk/clkmod/cx.rdx/pntr_gc_x(*)" TIG;
  1. Another option is to apply MAXDELAY constraints in the UCF. While these paths do not require an actual timing constraint, this can be done if necessary. The ideal timing constraint would be a MAXDELAY constraint set to twice the period of the slowest clock connected to the FIFO. For example (if the slowest clock has a period of 10ns):
NET "*BU2/U0/as.fgas/normgen.flblk/clkmod/cx.wrx/pntr_gc_x(*)" MAXDELAY = 20 ns;
NET "*BU2/U0/as.fgas/normgen.flblk/clkmod/cx.rdx/pntr_gc_x(*)" MAXDELAY = 20 ns;

To work around this issue (for Distributed Memory-based FIFOs):

  1. In addition to the options above for the other paths, the recommended option (besides ignoring the path in the report) is to apply a MAXDELAY of one clock period on the path from the DP output of the RAM to the output register clocked by RD_CLK.
AR# 30029
Date 01/28/2013
Status Active
Type General Article